1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a variable resistor circuit.
2. Description of the Related Art
FIG. 3 illustrates a semiconductor integrated circuit including a conventional variable resistor circuit. Referring to FIG. 3, a trimming circuit 351 includes PMOS transistors 310, 311, and 312, NPN transistors 313, 314, and 315, constant current sources 316, 317, and 318, control signal input pads 321, 322, and 323, and wirings D, E, and F. The PMOS transistors 310, 311, and 312 each have a source connected to a VDD terminal and a gate connected to a control terminal VG. The NPN transistor 313 has a base connected to the constant current source 316 and the control signal input pad 321, an emitter connected to a VSS terminal, and a collector connected to the wiring D and a drain of the PMOS transistor 310. The NPN transistor 314 has a base connected to the constant current source 317 and the control signal input pad 322, an emitter connected to the VSS terminal, and a collector connected to the wiring E and a drain of the PMOS transistor 311. The NPN transistor 315 has a base connected to the constant current source 318 and the control signal input pad 323, an emitter connected to the VSS terminal, and a collector connected to the wiring F and a drain of the PMOS transistor 312.
A constant voltage circuit 341 includes an amplifier 301, resistors 302 to 306, and NMOS transistors 307, 308, and 309. The resistors 302 to 306 together form an output voltage dividing circuit. The NMOS transistors 307, 308, and 309 have sources and drains which are connected in parallel to the resistors 303, 304, and 305, respectively. The source and the drain of the NMOS transistor 307 are connected across the resistor 303, and a gate thereof is connected to the wiring D. The source and the drain of the NMOS transistor 308 are connected across the resistor 304, and a gate thereof is connected to the wiring E. The source and the drain of the NMOS transistor 309 are connected across the resistor 305, and a gate thereof is connected to the wiring F. The amplifier 301 has a non-inverting input terminal connected to a Vref terminal. The resistor 302 has one terminal connected to an output of the amplifier 301 and a VR terminal, and another terminal connected to an inverting input terminal of the amplifier 301 and the resistor 303. The resistors 302 to 306 are connected in series.
The semiconductor integrated circuit including the conventional variable resistor circuit is a circuit capable of trimming an output voltage to be output from the output terminal VR by trimming a resistance of the variable resistor circuit. The resistors 303 to 305 are subjected to trimming. When the control signal input pads 321, 322, and 323 are open, respective collector voltages of the NPN transistors 313, 314, and 315 are Lo, and the NMOS transistors 307, 308, and 309 are OFF. In this state, the resistors 303 to 305 are not short-circuited but connected to other adjacent elements. When 0 V is applied to the control signal input pads 321, 322, and 323, the NPN transistors 313, 314, and 315 become an interrupted state. Accordingly, the collector voltages are changed to Hi, and the NMOS transistors 307, 308, and 309 are turned ON. In this state, the resistors 303 to 305 are short-circuited. This way, trimming can be performed (see, for example, Japanese Patent Application Laid-open No. Hei 10-335593 (FIG. 1)).
In the semiconductor integrated circuit including the conventional variable resistor circuit as configured above, there is an error in trimming amount depending on ON-state resistances of the NMOS transistors as switch elements. It is therefore difficult to trim the resistance with accuracy. Further, there is another problem that, even if the trimming is performed taking the ON-state resistances into account, the trimmed resistance has an error because of power supply voltage dependence or temperature dependence of the ON-state resistances. Still further, there is another problem that the layout area of the circuit is increased because it is necessary to increase the size of the NMOS transistors for reducing the ON-state resistances to reduce the influence of the ON-state resistances.